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<title>VRNDSCALEPD—Round Packed Float64 Values To Include A Given Number Of Fraction Bits </title></head>
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<h1>VRNDSCALEPD—Round Packed Float64 Values To Include A Given Number Of Fraction Bits</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.128.66.0F3A.W1 09 /r ib</p>
<p>VRNDSCALEPD xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Rounds packed double-precision floating point values in xmm2/m128/m64bcst to a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register. Under writemask.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F3A.W1 09 /r ib</p>
<p>VRNDSCALEPD ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Rounds packed double-precision floating point values in ymm2/m256/m64bcst to a number of fraction bits specified by the imm8 field. Stores the result in ymm1 register. Under writemask.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F3A.W1 09 /r ib</p>
<p>VRNDSCALEPD zmm1 {k1}{z}, zmm2/m512/m64bcst{sae}, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Rounds packed double-precision floating-point values in zmm2/m512/m64bcst to a number of fraction bits specified by the imm8 field. Stores the result in zmm1 register using writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>Imm8</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Round the double-precision floating-point values in the source operand by the rounding mode specified in the immediate operand (see Figure 5-29) and places the result in the destination operand.</p>
<p>The destination operand (the first operand) is a ZMM/YMM/XMM register conditionally updated according to the writemask. The source operand (the second operand) can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.</p>
<p>The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by imm8[7:4] (to be included in the result) and returns the result as a double-precision floating-point value.</p>
<p>It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by the imm8[7:4] value).</p>
<p>The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and shown in the “Immediate Control Description” figure below. Bit 3 of the immediate byte controls the processor behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Immediate control table below lists the encoded values for rounding-mode field).</p>
<p>The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an SNaN then it will be converted to a QNaN. If DAZ is set to ‘1 then denormals will be converted to zero before rounding.</p>
<p>The sign of the result of this instruction is preserved, including the sign of zero.</p>
<p>The formula of the operation on each data element for VRNDSCALEPD is</p>
<p>ROUND(x) = 2<sup>-M</sup>*Round_to_INT(x*2<sup>M</sup>, round_ctrl),</p>
<p>round_ctrl = imm[3:0];</p>
<p>M=imm[7:4];</p>
<p>The operation of x*2<sup>M</sup> is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).</p>
<p>VRNDSCALEPD is a more general form of the VEX-encoded VROUNDPD instruction. In VROUNDPD, the formula of the operation on each element is</p>
<p>ROUND(x) = Round_to_INT(x, round_ctrl),</p>
<p>round_ctrl = imm[3:0];</p>
<p>Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.</p>
<table>
<tr>
<td>
<p>7</p>
<p>imm8</p></td>
<td>
<p>6</p>
<p>Imm8[7:4] : Number of fixed points to preserve</p></td>
<td>5</td>
<td>
<p>4</p>
<p>Suppress Precision Exception: Imm8[3]</p>
<p>Imm8[3] = 0b : Use MXCSR exception mask</p>
<p>Imm8[3] = 1b : Suppress</p></td>
<td>3</td>
<td>
<p>2</p>
<p>Round Select: Imm8[2]</p></td>
<td>
<p>1</p>
<p>Imm8[2] = 0b : Use Imm8[1:0]</p>
<p>Imm8[2] = 1b : Use MXCSR</p></td>
<td>
<p>0</p>
<p>Imm8[1:0] = 00b : Round nearest even</p>
<p>Imm8[1:0] = 01b : Round down</p>
<p>Imm8[1:0] = 10b : Round up</p>
<p>Imm8[1:0] = 11b : Truncate</p></td></tr></table>
<table>
<tr>
<td></td>
<td></td>
<td>
<p>SPE</p>
<p>RS</p>
<p>Fixed point length</p></td>
<td>
<p>SPE</p>
<p>RS</p>
<p>Fixed point length</p></td></tr>
<tr>
<td>
<p>SPE</p>
<p>RS</p>
<p>Fixed point length</p></td>
<td>
<p>SPE</p>
<p>RS</p>
<p>Fixed point length</p></td>
<td>
<p>SPE</p>
<p>RS</p>
<p>Fixed point length</p></td>
<td>Round Control Override</td></tr></table>
<h3>Figure 5-29.  Imm8 Controls for VRNDSCALEPD/SD/PS/SS</h3>
<p>Handling of special case of input values are listed in Table 5-22.</p>
<h3>Table 5-22. VRNDSCALEPD/SD/PS/SS Special Cases</h3>
<table>
<tr>
<td></td>
<th>Returned value</th></tr>
<tr>
<th>Src1=±inf</th>
<td>Src1</td></tr>
<tr>
<th>Src1=±NAN</th>
<td>Src1 converted to QNAN</td></tr>
<tr>
<th>Src1=±0</th>
<td>Src1</td></tr></table>
<p><strong>Operation</strong></p>
<p>RoundToIntegerDP(SRC[63:0], imm8[7:0]) {</p>
<p>if (imm8[2] = 1)</p>
<p>rounding_direction (cid:197) MXCSR:RC</p>
<p>; get round control from MXCSR</p>
<p>else</p>
<p>rounding_direction (cid:197) imm8[1:0]</p>
<p>; get round control from imm8[1:0]</p>
<p>FI</p>
<p>M (cid:197) imm8[7:4]</p>
<p>; get the scaling factor</p>
<p>case (rounding_direction)</p>
<p>00: TMP[63:0] (cid:197) round_to_nearest_even_integer(2<sup>M</sup>*SRC[63:0])</p>
<p>01: TMP[63:0] (cid:197) round_to_equal_or_smaller_integer(2<sup>M</sup>*SRC[63:0])</p>
<p>10: TMP[63:0] (cid:197) round_to_equal_or_larger_integer(2<sup>M</sup>*SRC[63:0])</p>
<p>11: TMP[63:0] (cid:197) round_to_nearest_smallest_magnitude_integer(2<sup>M</sup>*SRC[63:0])</p>
<p>ESAC</p>
<p>Dest[63:0] (cid:197) 2<sup>-M</sup>* TMP[63:0]</p>
<p>; scale down back to 2<sup>-M</sup></p>
<p>if (imm8[3] = 0) Then</p>
<p>; check SPE</p>
<p>if (SRC[63:0] != Dest[63:0]) Then</p>
<p>; check precision lost</p>
<p>set_precision()</p>
<p>; set #PE</p>
<p>FI;</p>
<p>FI;</p>
<p>return(Dest[63:0])</p>
<p>}</p>
<p><strong>VRNDSCALEPD (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>IF *src is a memory operand*</p>
<p>THEN TMP_SRC (cid:197) BROADCAST64(SRC, VL, k1)</p>
<p>ELSE TMP_SRC (cid:197) SRC</p>
<p>FI;</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197) RoundToIntegerDP((TMP_SRC[i+63:i], imm8[7:0])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI;</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VRNDSCALEPD __m512d _mm512_roundscale_pd( __m512d a, int imm);</p>
<p>VRNDSCALEPD __m512d _mm512_roundscale_round_pd( __m512d a, int imm, int sae);</p>
<p>VRNDSCALEPD __m512d _mm512_mask_roundscale_pd(__m512d s, __mmask8 k, __m512d a, int imm);</p>
<p>VRNDSCALEPD __m512d _mm512_mask_roundscale_round_pd(__m512d s, __mmask8 k, __m512d a, int imm, int sae);</p>
<p>VRNDSCALEPD __m512d _mm512_maskz_roundscale_pd( __mmask8 k, __m512d a, int imm);</p>
<p>VRNDSCALEPD __m512d _mm512_maskz_roundscale_round_pd( __mmask8 k, __m512d a, int imm, int sae);</p>
<p>VRNDSCALEPD __m256d _mm256_roundscale_pd( __m256d a, int imm);</p>
<p>VRNDSCALEPD __m256d _mm256_mask_roundscale_pd(__m256d s, __mmask8 k, __m256d a, int imm);</p>
<p>VRNDSCALEPD __m256d _mm256_maskz_roundscale_pd( __mmask8 k, __m256d a, int imm);</p>
<p>VRNDSCALEPD __m128d _mm_roundscale_pd( __m128d a, int imm);</p>
<p>VRNDSCALEPD __m128d _mm_mask_roundscale_pd(__m128d s, __mmask8 k, __m128d a, int imm);</p>
<p>VRNDSCALEPD __m128d _mm_maskz_roundscale_pd( __mmask8 k, __m128d a, int imm);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Invalid, Precision</p>
<p>If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).</p>
<p><strong>Other Exceptions</strong></p>
<p>See Exceptions Type E2.</p></body></html>